Our invention relates to a method of fabricating a semiconductor device with a base region having a deep portion for reducing parasitic device currents, and, more particularly, to such method wherein an electrical short (i.e., short circuit) is formed across a P-N junction that is located between the base region and a region of opposite dopant type, the electrical short assisting in reducing parasitic currents in the device.
A prior art semiconductor device, comprising a MOSFET, is described in an article by G. Bell and W. Ladenhauf, "SIPMOS Technology, an Example of VLSI Precision Realized With Standard LSI for Power Transistors", Siemens Forsch.-u.Entwickl.-Ber. Bd.9(1980) Nr.4, pages 190-194 (FIG. 7). The MOSFET therein described includes N.sup.+ and N.sup.- drain regions (the supercripts "+" and "-" referring to relative doping concentrations), and N.sup.+ source region, and a P type base region. The MOSFET is of the enhancement mode type; that is, an N type conduction channel is induced within part of the P type base region only when the gate of the MOSFET is biased above a threshold voltage. The P type base region contains a deep P.sup.+ portion as well as a shallow P portion. An electrical short is formed across the P-N junction extant between the N.sup.+ source region and P type base region to suppress parasitic current that would otherwise result if such P-N junction were to become biased in a manner whereby the N.sup.+ source injected electrons into the P type base region. The deep P.sup.+ portion of the P type base region helps to prevent the N.sup.+ source region from injecting electrons into the P type base region.
In the method of fabricating the prior art MOSFET, as described in the foregoing article, the deep P.sup.+ portion of the P type base region is diffused into a wafer of semiconductor material through a first window of a diffusion mask. Then the shallower P portion of the P type base region is diffused into the wafer through a second window of a second diffusion mask, such second window being larger than the first window and centered about the first window. Thereafter, the N.sup.+ source region is diffused into the wafer through the second window. Due to processing constraints, the thus-formed N.sup.+ source region covers the deep P.sup.+ portion, leaving no portion of the P-N junction extant between the N.sup.+ source region and the P.sup.+ deep portion exposed at the upper surface of the wafer. As a consequence, the N.sup.+ source region must be etched through to the deep P.sup.+ portion in order to expose part of such P-N junction before an electrical short can be formed across the P-N junction.
The presence of the foregoing etching step increases the complexity of fabricating a MOSFET by requiring a photolithographic mask to be meticulously aligned over previously-formed features of the MOSFET. The inclusion of such alignment procedure decreases the yield of operable MOSFETs and, hence, increases their cost.